Title :
Strategies for CMOS/BiCMOS gate usage on sea-of-gates arrays
Author :
Duchene, P.P. ; Declercq, M.J.
Author_Institution :
Electron Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
Abstract :
Strategies for merging CMOS and BiCMOS gates on a sea-of-gates (SOG) array are analyzed. Starting from theoretical and experimental distributions for load capacitance and gate complexity, the average delay and area and the optimal percentage of each gate type can be calculated. From those results, the optimal bipolar-to-MOS count ratio of a BiCMOS SOG master can be derived. Advanced gate usage strategies mixing simple and buffered CMOS and BiCMOS gate configurations are shown to be significantly superior in terms of speed and density. For typical capacitance distributions, the speed advantage can be as high as 70% compared to a pure BiCMOS solution
Keywords :
BIMOS integrated circuits; CMOS integrated circuits; logic arrays; logic gates; CMOS/BiCMOS gate usage; SOG; average delay; bipolar-to-MOS count ratio; capacitance distributions; density; gate complexity; gate usage strategies; load capacitance; sea-of-gates arrays; speed; Application specific integrated circuits; BiCMOS integrated circuits; Delay; Design optimization; Distribution functions; Integrated circuit technology; MOSFETs; Probability; Random variables; SPICE;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.163985
