FP-map-an approach to the functional pipelining of embedded programs

Practice shows that increasing the amount of instruction level parallelism offered by an architecture (like adding instruction slots to VLIW instructions) does not necessarily lead to significant performance gains. Instead, high hardware costs and inefficient use of this hardware may occur. Mapping embedded applications onto multiprocessor systems forms a very interesting extension to ILP. We propose a functional pipelining approach to the mapping of embedded programs written in ANSI C onto a pipeline of application specific processors. Our novel functional pipelining algorithm has low computational complexity and was especially developed to form the parallelization engine of a (semi) automatic system for multiprocessor embedded system design. The paper explains the proposed algorithm and demonstrates its applicability