Synthesis of self-testing finite state machines from high-level specification

Current approaches to self test consist of adding hardware to the already synthesized circuits to transform them into autonomous finite state machines. If the circuit´s own function is used for test generation and or data compression, then the fault coverage and aliasing properties have to be obtained by simulation. In this paper, we give a function-level specification for the self-test problem. In the self-test mode, all primary inputs and outputs are latched. The circuit behaves as an autonomous finite-state machine, which executes an Euler walk of all states. Thus, each state is visited exactly once, with all states forming a closed path in the state transition graph of the test machine. This function is embedded in the high-level description of the given finite state machine. The self-test hardware thus undergoes the same optimization process as the machine hardware, with a chance of better area/timing optimization. Up to 100% fault coverage against all single/multiple faults can be achieved if the appropriate synthesis/optimization tools are used. On completion of self-test the signature, consisting of the states of all flip-flops, is shown to have an aliasing probability 2^-m when the circuit has m flip-flops and the fault corrupts a single state-transition