A low-complexity B-spline based digital sample rate conversion circuit architecture

Author

Lin, Ching-Chi ; Chi, Rsiang-Feng

Author_Institution

Dept. of Commun. Eng., National Chiao-Tung Univ., Hsinchu, Taiwan

Volume

2

fYear

2005

fDate

14-15 July 2005

Firstpage

505

Abstract

This paper presents low-complexity digital sample rate conversion (SRC) circuit architecture with arbitrary factor conversion ratio. The strategy in deciding SRC system parameters is given to guarantee that both the anti-imaging and the anti-aliasing requirements can be satisfied. The significant reduction in the complexity of the proposed structure allows simple VLSI implementation without affecting the performance. A parallel cascaded integrator comb (CIC) filter circuit without high intermediate sample rate and a multiplier-less linear interpolator are also developed to obtain a cost-effective and high-speed SRC circuit.

Keywords

VLSI; circuit complexity; comb filters; digital integrated circuits; interpolation; splines (mathematics); B-spline based SRC circuit; VLSI implementation; anti-aliasing requirement; anti-imaging requirement; arbitrary factor conversion ratio; cascaded integrator comb filter; digital sample rate conversion circuit; linear interpolator; Circuits; Costs; Digital filters; Filtering; Finite impulse response filter; Hardware; Interpolation; Polynomials; Spline; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on

Print_ISBN

0-7803-9029-6

Type

conf

DOI

10.1109/ISSCS.2005.1511288

Filename

1511288