Performance driven BIST technique for random logic

Author

Njinda, Charles A. ; Kaul, Neeraj

Author_Institution

Adv. Micro Devices Inc., Sunnyvale, CA, USA

fYear

1995

fDate

21-25 Oct 1995

Firstpage

524

Lastpage

533

Abstract

Performance degradation due to insertion of BIST logic into high-speed designs has been analyzed. A framework to introduce BIST into random logic circuits, without causing timing violations has been proposed. Various heuristics for selecting flip-flops for BIST have been developed and studied in detail. Experimental results indicate an improvement in performance while optimizing fault coverage and area overhead

Keywords

VLSI; automatic testing; built-in self test; flip-flops; integrated circuit testing; logic testing; sequential circuits; timing; area overhead; fault coverage; flip-flops; heuristics; high-speed designs; performance degradation; performance driven BIST technique; random logic; timing violations; Built-in self-test; Circuit testing; Costs; Design for testability; Logic design; Logic devices; Logic testing; Registers; Sequential analysis; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529880

Filename

529880

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2057943