A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level

Author

Segura, J. ; De Benito, C. ; Rubio, A. ; Hawkins, C.F.

Author_Institution

Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain

fYear

1995

fDate

21-25 Oct 1995

Firstpage

544

Lastpage

551

Abstract

The properties of Gate Oxide Short defects (GOS) in CMOS circuits are investigated identifying the most relevant parameters that determine the behavior of a defective device. Electrical models of the defect are developed and compared with experimentation. Depending upon location and transistor type, GOSs are resistive, diode, parasitic MOSFET or parasitic BJT. We also investigate the necessary conditions to detect a GOS at the circuit level, providing the bases for an efficient ATPG approach

Keywords

CMOS integrated circuits; MOSFET; automatic testing; integrated circuit modelling; integrated circuit testing; ATPG approach; CMOS circuits; GOS defects; MOS transistors; circuit level; defective device behaviour; diode defects; electrical models; gate oxide short defects; parasitic BJT; parasitic MOSFET; resistive defects; testing implications; Circuit testing; Diodes; Doping; Electric breakdown; MOSFET circuits; Physics; Semiconductor device modeling; Semiconductor process modeling; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529882

Filename

529882