Title :
A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture
Author :
Holland, P.M. ; Elwin, M.P. ; Batcup, S. ; Zhou, Z. ; Igic, P.M.
Author_Institution :
Swansea Univ., Swansea
Abstract :
A study of the latch-up robustness for a new power IC technology involving Si substrate/wafer modifications is presented in this paper. The results shown confirm that for dual-well CMOS technologies, changes in the substrate/epitaxial layer structure are a satisfactory way of improving power IC process capabilities without compromising the CMOS performance. Both simulation and experimental results are presented.
Keywords :
CMOS integrated circuits; buffer circuits; epitaxial layers; power integrated circuits; latch-up robustness; p-buffer CMOS; power IC technology architecture; substrate-epitaxial layer structure; wafer modifications; CMOS process; CMOS technology; Epitaxial layers; Failure analysis; Integrated circuit reliability; Power integrated circuits; Power transistors; Robustness; Silicon; Substrates;
Conference_Titel :
Microelectronics, 2008. MIEL 2008. 26th International Conference on
Conference_Location :
Nis
Print_ISBN :
978-1-4244-1881-7
Electronic_ISBN :
978-1-4244-1882-4
DOI :
10.1109/ICMEL.2008.4559252
