An improved DFT based method for phasor estimation in fault scenarios

This paper presents a new methodology for phasor estimation in the presence of exponentially DC decay (DC offset) and odd harmonics in the signal. The estimations are performed on a half cycle plus four samples of the fundamental component of the system. The method uses digital signal processing techniques such as windowing, DFT (Discrete Fourier Transform) modulation and look up tables (LUT). The performance of the proposed method is compared with others methods presented in the literature. The results from simulation showed that the proposed method has a better performance that the others. In addition to the floating-point implementation, the proposed method was implemented in a reconfigurable hardware platform, FPGA (Field Programmable Gate Array) using fixed-point arithmetic.