Optimal multiple chain relay testing scheme for MCMs on large area substrates

One of the key factors that has prevented multi-chip modules (MCMs) from gaining mass acceptance in the electronics industry is their high cost. Often contributing to as much as 40% of this cost is the cost of testing the MCMs after they are manufactured. In this paper, we address the problem of testing MCMs fabricated on large area substrates, analogous to the way ICs are manufactured on silicon wafers (this reduces manufacturing cost). Our objective is to reduce the cost of testing MCMs by parallelizing the test process. In this paper we propose a novel relay propagation scheme in which the test stimuli and their correct responses are scanned in an interleaved and pipelined manner into the MCMs. Comparison of the observed and the correct response for each test vector is performed locally at each MCM. It is shown that our scheme results in drastic speedup over conventional boundary scan based testing. We also show that the test time using our testing methodology asymptotically approaches the optimal with the use of larger numbers of test chains