Analytical delay computation for arbitrary distributed RLC trees

As feature size decreases and circuit size and complexity increases, interconnect plays a dominating role in determining the overall circuit performance, reliability and cost. With decreasing feature sizes, the delay due to the resistance and capacitance of on-chip interconnects increasingly dominates the delay due to transistors. In this paper, we present a closed-form delay calculation approach for distributed RLC interconnect trees that addresses shortcomings with past interconnect models.