Title :
Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks
Author :
Shimizu, Sho ; Kihara, Taku ; Arakawa, Yutaka ; Yamanaka, Naoaki ; Shiba, Kosuke
Author_Institution :
Keio Univ., Kawasaki
Abstract :
A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.
Keywords :
multiprotocol label switching; telecommunication traffic; GMPLS networks; hardware based scalable path computation engine; multilayer traffic engineering; parallel data-flow hardware; Computer networks; Concurrent computing; Hardware; Network topology; Nonhomogeneous media; Optical fiber networks; Parallel processing; Routing; Search engines; Telecommunication traffic;
Conference_Titel :
Optical Communication, 2008. ECOC 2008. 34th European Conference on
Conference_Location :
Brussels
Print_ISBN :
978-1-4244-2227-2
Electronic_ISBN :
978-1-4244-2228-9
DOI :
10.1109/ECOC.2008.4729415
