Title :
Improved instruction fetching with a new block-based cache scheme
Author :
Beg, Azam ; Chu, Yul
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
Instruction fetch speeds are improved by using cache schemes that are based on dynamic flow of program instructions. Variable-sized block cache (VSBC) is a new instruction scheme that stores basic code blocks and their boundaries as traces. Current trace- or block-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. The studies done so far, in single- and multi-threaded environments, have shown improvements in trace miss rate. Other aspects of VSBC performance such as trace length and latency are being studied.
Keywords :
block codes; cache storage; memory architecture; multi-threading; block-based cache scheme; code block; dynamic flow; instruction fetching; instruction scheme; multithreaded environment; program instruction; single-threaded environment; trace latency; trace length; trace miss rate; trace-based cache scheme; variable-sized block cache; Bandwidth; Cache storage; Computer architecture; Delay; Hardware; Multilevel systems; Radio access networks; USA Councils; Yarn;
Conference_Titel :
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on
Print_ISBN :
0-7803-9029-6
DOI :
10.1109/ISSCS.2005.1511353