• DocumentCode
    2059178
  • Title

    A pipelined 9-stage video-rate analog-to-digital converter

  • Author

    Lewis, Stephen H. ; Fetterman, H. Scott ; Gross, George F., Jr. ; Ramachandran, R. ; Viswanathan, T.R.

  • Author_Institution
    AT&T Bell Lab., Allentown, PA, USA
  • fYear
    1991
  • fDate
    12-15 May 1991
  • Abstract
    The authors describe a nine-stage, pipelined, video-rate, analog-to-digital converter (ADC) in a 0.9-μm CMOS technology. At a conversion rate of 20 Msamples/s, the converter has 10-b resolution, 56-dB signal-to-noise-and-distortion ratio (SNDR) with a 100-kHz input, and 54-dB SNDR with a 5-MHz input. It occupies 9.3 mm2 and dissipates 300 mW. The key innovation in this ADC is the improved correction algorithm, which requires one fewer comparator per stage than used in traditional architectures
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.9 micron; 300 mW; ADC; CMOS; analog-to-digital converter; correction algorithm; nine-stage; pipelined; video-rate; Analog-digital conversion; CMOS technology; Costs; Distortion; Error correction; Logic; Operational amplifiers; Power dissipation; Redundancy; Signal resolution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0015-7
  • Type

    conf

  • DOI
    10.1109/CICC.1991.163994
  • Filename
    163994
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2059178