On performance of series connected CMOS vertical hall devices

Series connected (stacked) CMOS vertical Hall devices were analyzed on the basis of performance of a single five contacts device biased at different common mode voltages with respect to the substrate. The uneven influence of junction field effect on residual offset voltage, sensitivity and residual offset equivalent magnetic field was studied. It was shown that though junction field effect leads to some increase in offset voltage for devices with higher common mode, this effect can be minimized through suitable biasing.