Event driven mixed signal modeling techniques for System-in-Package functional verification

Developing complex mixed-signal System-in-Package (SiP) chip-sets or Systems-on-Chip (SoC) typically involves parallel analog and digital IC development, where verification engineers can expect to encounter disconnects between the design automation flows, user proficiencies, and IC release cycles. Verifying the SiP chip-set prior to manufacturing is the key milestone where these disconnects are resolved. Presented is a unique modeling, simulation and verification method which bridges these gaps much earlier in the design process. As an illustrative example the verification of a complex SiP for space applications is presented.