New concepts of worst-case delay evaluation in asynchronous VLSI SoC

Estimation of asynchronous circuit performances, such as speed, is one of the major issues that make that design style still less popular than it deserves to be. Evaluating the worst case delays in the paths of an asynchronous circuit using a simple logic simulator would be very useful in overcoming this problem. In this paper a method for timing analysis of the asynchronous non-sequential circuits using a VHDL simulator is presented. With an appropriate extension of the standard logic simulation process, all worst case delays for all paths in a digital circuit with only one run of the simulation can be obtained. High levels of accuracy are achieved using different gate modelling and statistical analysis of the results. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.