DocumentCode
2059601
Title
Design for testability for SoC based on IDDQ scanning
Author
Sokolovic, Miljana ; Petkovic, Predrag ; Litovski, Vanco
Author_Institution
Dept. of Eiectron., Nis Univ., Nis
fYear
2008
fDate
11-14 May 2008
Firstpage
407
Lastpage
410
Abstract
One DFT solution for systems on chip, based on IDDQ measuring concept is presented in this paper. The application of Reconfigurable neurai networks off chip enables also good diagnostics capabilities. The solution is to be implemented in few digital blocks of the tree phase power meter IC and realized using CMOS035 technology. The simulation results obtained using Cadence Virtuoso show good performances of the solution.
Keywords
CMOS integrated circuits; design for testability; integrated circuit testing; neural nets; system-on-chip; CMOS035 technology; Cadence Virtuoso; IDDQ scanning; SoC; design for testability; digital blocks; reconfigurable neural networks; tree phase power meter IC; CMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Current measurement; Design for testability; Electronic equipment testing; Fault detection; Integrated circuit measurements; Observability;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2008. MIEL 2008. 26th International Conference on
Conference_Location
Nis
Print_ISBN
978-1-4244-1881-7
Electronic_ISBN
978-1-4244-1882-4
Type
conf
DOI
10.1109/ICMEL.2008.4559307
Filename
4559307
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