Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits

In this work, we present a new approach for the pseudo-exhaustive BIST of synchronous sequential circuits. We first give a characterization of the flip-flops that cause the unbalanced structure of the acyclic circuit using peripheral retiming techniques, and, consequently, both logic optimization and balancing problem are considered and solved in the same phase. Second, the balancing solution is considered as a first step of the partitioning problem. For the remaining balanced circuit, the segmentation edges are selected such that there is a retiming minimizing the number of segmentation cells in the retimed circuit. Experimental results show that our approach significantly reduces the hardware overhead relative to the existing approaches