DocumentCode
2059747
Title
Software environment for synthesis of testable FSM through decomposition
Author
Devadze, S. ; Sudnitson, A.
Author_Institution
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn
fYear
2008
fDate
11-14 May 2008
Firstpage
433
Lastpage
436
Abstract
This paper presents a method and software for constructing of testabie finite state machines (FSM). The proposed method of impiementing test for FSM has severaf advantages in comparison with common soiutions. However, this method imposes some constraints on FSM synthesis process, which can be satisfied by using specific decomposition technique. The presented software environment (caifed D&S) is capabie to perform various kinds of FSM decomposition and synthesis, inciuding the one needed for constructing of testabie FSM.
Keywords
built-in self test; finite state machines; logic CAD; FSM decomposition; finite state machines; software environment; testable FSM; Automata; Built-in self-test; Circuit synthesis; Circuit testing; Design optimization; Logic testing; Pattern analysis; Performance evaluation; Software testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2008. MIEL 2008. 26th International Conference on
Conference_Location
Nis
Print_ISBN
978-1-4244-1881-7
Electronic_ISBN
978-1-4244-1882-4
Type
conf
DOI
10.1109/ICMEL.2008.4559314
Filename
4559314
Link To Document