A review of test techniques for RFIC’s and an application of a proposed approach in a 1.9-GHz CMOS mixer

In this paper test techniques for RFICs are presented. A Built-In Test (BIT) circuit is appiied for a 1.9-GHz double balanced Gilbert-cell CMOS active mixer. The BIT circuit operation is based on the observation that the presence of catastrophic faults, like resistive bridgings, shorts and opens, or parametric faults, result in the attenuation of the output voltage amlitude (gain reduction). The BIT circuit along with an active down-conversion mixer have been designed in a 90 nm UMC CMOS technology to evaluate the efficiency of the proposed approach and experimental results are presented.