DocumentCode
2059869
Title
A defect-tolerant memory architecture for molecular electronics
Author
Lee, Myung-Hyun ; Kim, Young Kwan ; Choi, Yoon-Hwa
Author_Institution
Dept. of Comput. Eng., Hongik Univ., Seoul, South Korea
Volume
2
fYear
2003
fDate
12-14 Aug. 2003
Firstpage
713
Abstract
This paper presents a defect-tolerant memory architecture for molecular electronics. An augmented crossbar-based memory, where molecules are sandwiched between nanowires, is used as a model to achieve defect tolerance. Defects in the logic circuits for addressing memory are also taken into account. The number of spare rows and columns to form a functioning memory is estimated by computer simulation for various values of defect rate and memory size.
Keywords
demultiplexing equipment; digital simulation; logic circuits; memory architecture; molecular electronics; nanowires; addressing memory; augmented crossbar based memory; computer simulation; defect rate; defect tolerant memory architecture; logic circuits; memory size; molecular electronics; nanowires; spare rows; Assembly; Circuit faults; Electric resistance; Logic circuits; Logic devices; Memory architecture; Molecular electronics; Nanowires; Switches; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on
Print_ISBN
0-7803-7976-4
Type
conf
DOI
10.1109/NANO.2003.1231012
Filename
1231012
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