Title :
NCL Implementation of Dual-Rail 2S Complement 8Ã\x978 Booth2 Multiplier using Static and Semi-Static Primitives
Author :
Joshi, M.V. ; Gosavi, S. ; Jegadeesan, V. ; Basu, A. ; Jaiswal, S. ; Al-Assadi, W.K. ; Smith, S.C.
Author_Institution :
Univ. of Missouri -Rolla, Rolla
Abstract :
In this work, we use static and semi-static versions of NULL Convention Logic (NCL) primitives (i.e., threshold gates) to implement a dual-rail 8times8 2s complement multiplier using the Modified Booth2 algorithm for partial product generation and a Wallace tree for partial product summation. We establish the multiplier´s functionality utilizing VHDL-based simulations of the gate-level structural design. The design is then implemented at the transistor-level and layout-level using both static and semi-static threshold gates, for a 1.8V 0.18mum TSMC CMOS process; and these two implementations are compared in terms of area, power, and speed.
Keywords :
CMOS logic circuits; circuit simulation; hardware description languages; logic design; multiplying circuits; threshold logic; Booth2 multiplier; NCL implementation; NULL Convention Logic primitives; TSMC CMOS process; VHDL-based simulations; Wallace tree; complement multiplier; gate-level structural design; partial product generation; partial product summation; semi-static primitives; threshold gates; Algorithm design and analysis; Boolean functions; Circuit simulation; Clocks; Crosstalk; Delay; Electronics industry; Logic circuits; Rails; Timing;
Conference_Titel :
Region 5 Technical Conference, 2007 IEEE
Conference_Location :
Fayetteville, AR
Print_ISBN :
978-1-4244-1280-8
Electronic_ISBN :
978-1-4244-1280-8
DOI :
10.1109/TPSD.2007.4380352
