Title :
A routing testing of a VLSI massively parallel machine based on IEEE 1149.1
Author :
Aktouf, C. ; Robach, C. ; Marinescu, A.
Author_Institution :
LGI-IMAG, Grenoble, France
Abstract :
A practical testing strategy is presented for locating faults occurring on both cells´ routing parts and internal physical lines within a 2D massively parallel machine. We present first an approach which does not consider all practical constraints. Then, an approach based on IEEE 1149.1 standard is studied and its efficiency is illustrated. The results obtained are given
Keywords :
VLSI; automatic testing; computer testing; network routing; parallel machines; 2D massively parallel machine; IEEE 1149.1 standard; MIMD machines; VLSI; fault location; internal physical lines; routing testing; testing strategy; Circuit faults; Circuit testing; Costs; Multiprocessing systems; Parallel architectures; Parallel machines; Probes; Read-write memory; Routing; Very large scale integration;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529909
