Title :
Self-aligned n-shaped source/drain ultra-thin SOI MOSFETs
Author :
Eng, Yi-Chuen ; Lin, Jyi-Tsong ; Lin, Po-Hsieh ; Huang, Hau-Yuan ; Kang, Shiang-Shi ; Kao, Kung-Kai ; Lin, Jeng-Da ; Tseng, Yi-Ming ; Tsai, Ying-Chieh
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ. (NSYSU EE), Kaohsiung
Abstract :
What is silicon-on-insulator (SOI)? Why SOI? Because of the excellent short-channel effects (SCEs) immunity, SOI group is generally considered to be a very strong candidate in the end of the CMOS (complementary metal-oxide semiconductor) scaling, as compared to bulk silicon. This paper aims to propose a novel device architecture namely self-aligned (SA) Pi-shaped source/drain ultra-thin SOI MOS field-effect transistor (Pi-S/D UTSOI MOSFET). Although this approach is based on simulation, numerical simulations, it demonstrates the trends of electrical characteristics in the proposed structure. This work also illustrates the process simulation and the tradeoff between the self-heating and the short-channel behaviors which are two important attributes of the future scaled-down UTSOI devices.
Keywords :
MOSFET; semiconductor device models; silicon-on-insulator; thin film transistors; CMOS; MOSFET; Si; complementary metal-oxide semiconductor; field-effect transistor; self-heating; short-channel behaviors; short-channel effects; silicon-on-insulator; source-drain ultra-thin SOI MOS field-effect transistor; Chemical vapor deposition; Electric variables; Etching; FETs; Lattices; MOS devices; MOSFETs; Numerical simulation; Silicon on insulator technology; Thermal degradation;
Conference_Titel :
Microelectronics, 2008. MIEL 2008. 26th International Conference on
Conference_Location :
Nis
Print_ISBN :
978-1-4244-1881-7
Electronic_ISBN :
978-1-4244-1882-4
DOI :
10.1109/ICMEL.2008.4559327