Title :
Source/drain-tied bottom gate MOSFET for device reliability improvement
Author :
Lin, Jeng-Da ; Lin, Jyi-Tsong ; Lin, Po-Hsieh ; Kao, Kung-Kai ; Kang, Shiang-Shi ; Eng, Yi-Chuen ; Tseng, Yi-Ming
Author_Institution :
Dept. of E E, Nat. Sun Yat-Sen Univ., Kaohsiung
Abstract :
The paper presents a non-classical architecture called the bottom gate MOSFET with source/drain tie (S/D-tied BG) to improve device reliability. S/D-tied BG MOSFET not only effectively reduce the effects of self-heating but also slightly suppress the short-channel effects.
Keywords :
MOSFET; semiconductor device models; semiconductor device reliability; device reliability improvement; self-heating; short-channel effects; source/drain-tied bottom gate MOSFET; threshold voltage; Degradation; Dry etching; FETs; Immune system; MOSFET circuits; Microelectronics; Parasitic capacitance; Region 5; Silicon on insulator technology; Wet etching;
Conference_Titel :
Microelectronics, 2008. MIEL 2008. 26th International Conference on
Conference_Location :
Nis
Print_ISBN :
978-1-4244-1881-7
Electronic_ISBN :
978-1-4244-1882-4
DOI :
10.1109/ICMEL.2008.4559331
