Abstract :
This paper describes work regarding improvements in boundary scan cell design. The results of this work provide an innovative way to implement boundary scan cells (BSCs) on IC input, output, and input/output (I/O) pins. The new cell designs provide; (1) reduced cell size, (2) reduced signalling delay, (3) support for IDDQ testing, (4) protection of output buffers in the presence of shorts, and (5) a method of safely testing newly assembled boards
Keywords :
IEEE standards; automatic testing; boundary scan testing; design for testability; fault diagnosis; integrated circuit testing; logic testing; I/O pins; IDDQ testing support; IC input; IC output; IEEE 1149.1; boundary scan cell design; functional core logic; output buffers protection; reduced cell size; reduced signalling delay; shared resource boundary scan; shorts; Assembly; Circuit testing; Clamps; Delay; Instruments; Integrated circuit testing; Pins; Protection; Signal design; Standards Working Groups;
