Title :
RFIC Design Methodology: Functional Verification
Author_Institution :
Cadence Design Syst., Inc., San Jose
Abstract :
Full-chip functional verification for RF-A/MS (analog mixed-signal) applications is not only new as a "design methodology process" to some design organizations; but, is fast becoming a "must have" verification as a final tape-out simulation sign-off. Today\´s wireless industry, due to tight schedule demands and short product life-cycles, requires that a RFIC development group deliver "1st pass functional silicon." Then, when functional RFIC silicon is produced, minor design changes (minimal mask-layer changes) needed to meet performance specifications can be accommodated within a wireless product schedule.
Keywords :
radiofrequency integrated circuits; RFIC design methodology; Circuit synthesis; Design automation; Design methodology; Hardware design languages; Job shop scheduling; Process design; Radio frequency; Radiofrequency integrated circuits; Silicon; Solid modeling;
Conference_Titel :
Region 5 Technical Conference, 2007 IEEE
Conference_Location :
Fayetteville, AR
Print_ISBN :
978-1-4244-1280-8
Electronic_ISBN :
978-1-4244-1280-8
DOI :
10.1109/TPSD.2007.4380363
