Model based analysis of electrical and wear-out characteristics of 7 nm thin Ta2O5/SiOxNy stacks on Si

In this work 7 nm thin Ta₂O₅/SiO_xN_y insulating stacks on Si were studied by a combination of C-V If and leakage current (I-V) measurements, based on the comprehensive model involving different conduction mechanisms in Ta₂O₅ and the interfacial SiO_xN_y layer. Equivalent oxide thickness (EOT) was determined using the extrapolation method for leaky high-k dielectrics proposed by Kar. Interface state densities were determined from the hf C-V characteristics by a standard method. Degradation after constant current stress (10 mA/cm², 100 s) was analyzed in terms of oxide charge build-up, interface states density (D_it) generation and consumption of the interfacial layer. No significant variation of D_it with the stress was observed - midgap values (D_itm) for both fresh and stressed samples are close to 5times10¹² eV^-1cm^-2. The observed decrease in interface charge (QA is very small and could be attributed to the interfacial layer consumption. Fixed positive oxide charge increases for a small but significant amount of 4times10¹¹ cm^-2. The most important variation with the stress is observed in the effective interfacial layer thickness (d_IL); it decreased for 0.12 nm as a result of the stress, leading to a decrease ofthe EOT for 0.10 nm, having that the dielectric constant of the interfacial SiO_xN_y layer is higher than that of the SiO₂ layer. Hence, the interfacial layer consumption is found to be the dominant wearout mode.