DocumentCode
2060661
Title
Finding I/O faults on in-circuit ICs using parasitic transistor tests
Author
Ferguson, Jack
Author_Institution
ITA Corp., USA
fYear
1995
fDate
21-25 Oct 1995
Firstpage
926
Abstract
With the growing use of surface mount technologies, continued reduction of lead spacing for mounting IC devices on circuit boards, and the increase in pin counts on packages well into the hundreds for many of today´s complex ASICs, the probability for faults to exist goes up dramatically. Conversely, the ability for conventional in-circuit functional test techniques to effectively detect, let alone isolate, these faults is just as dramatically going down. A vectorless test technique has been developed that uses a simple transistor test to detect and isolate I/O related faults on all types of ICs, from simple devices to complex ASICs
Keywords
application specific integrated circuits; fault location; integrated circuit testing; ASIC; I/O faults; complex ASIC; conventional in-circuit functional test; in-circuit IC; mounting; packages; parasitic transistor tests; pin counts; probability; surface mount technologies; transistor test; vectorless test; Circuit faults; Circuit testing; Costs; Current measurement; Electrical fault detection; Fault detection; Integrated circuit testing; Lifting equipment; Performance evaluation; Pins;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1995. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2992-9
Type
conf
DOI
10.1109/TEST.1995.529935
Filename
529935
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