A unified framework for design validation and manufacturing test

New approaches to address the difficult problems in test are necessary if its current status as a major bottleneck in the production of quality integrated circuits is to be changed. The authors propose a new direction for solving the test problem using powerful methods already employed for the formal verification of large circuits. More specifically, they discuss how abstraction techniques can assist conventional ATPG tools when attacking hard to detect faults. The same abstractions can also be used in design verification to increase the level of confidence in a design following simulation, by providing a meaningful measure of the coverage achieved by the verification vectors. In this sense, the authors´ approach is geared toward providing a unified fled framework for design validation and manufacturing test