• DocumentCode
    2060760
  • Title

    Implementation of Static and Semi-Static Versions of a Bit-Wise Pipelined Dual-Rail NCL 2S Complement Multiplier

  • Author

    Sankar, R. ; Kadiyala, V. ; Bonam, R. ; Kumar, S. ; Mohan, S. ; Kacani, F. ; Al-Assadi, Waleed K. ; Smith, S.C.

  • Author_Institution
    University of Missouri - Rolla, Department of Electrical and Computer Engineering, 1870 Miner Circle, Rolla, MO 65409
  • fYear
    2007
  • fDate
    20-22 April 2007
  • Firstpage
    228
  • Lastpage
    233
  • Abstract
    This paper focuses on implementing a 2s complement 8×8 dual-rail bit-wise pipelined multiplier using the asynchronous NULL Convention Logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18¿m TSMC CMOS process. The multiplier is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.
  • Keywords
    Boolean functions; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Computational modeling; Delay; Libraries; Rails; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Region 5 Technical Conference, 2007 IEEE
  • Conference_Location
    Fayetteville, AR, USA
  • Print_ISBN
    978-1-4244-1280-8
  • Electronic_ISBN
    978-1-4244-1280-8
  • Type

    conf

  • DOI
    10.1109/TPSD.2007.4380386
  • Filename
    4380386
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2060760