An attempt to completely utilize the bandwidth capability of PCI-X 133 MHz devices in a 66 MHz PCI-X local bus

The author presents a variation of the PCI-X 1.0 protocol which would prevent loss of valuable bandwidth in cases of transactions between two PCI-X-133 MHz capable devices present in a local bus operating at 66 MHz (due to the presence of at least one PCI-X 66 MHz device on the bus). In the conventional PCI-X protocol, there is no way in which transactions between two PCI-X 133 MHz devices can happen at 133 MHz when at least one PCI-X 66 MHz device is also present on the bus. A variation of the PCI-X protocol presented will eliminate the above limitation, enabling high speed devices to utilize their bandwidth capability to the maximum. The signalling scheme presented needs minimum changes to the PCI-X 1.0 version of the protocol and leads to bandwidth savings nearing 50% and a bus utilization factor nearing 100%.