DocumentCode
2061101
Title
Static charge decay analysis of MOS circuits
Author
Bischoff, Gabriel ; Razdan, R.
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1991
fDate
12-15 May 1991
Abstract
It is shown how symbolic analysis provides a practical solution to the charge decay verification problem and overcomes the uncertainty of pattern dependent verifications. The symbolic approach was successfully used to verify large CMOS VLSI designs for charge decay
Keywords
CMOS integrated circuits; MOS integrated circuits; VLSI; circuit analysis computing; ANAMOS; CMOS VLSI designs; MOS circuits; charge decay verification; static charge decay analysis; symbolic analysis; CMOS logic circuits; Circuit analysis; Circuit simulation; Computational modeling; Discrete event simulation; Logic circuits; Logic design; Pattern analysis; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0015-7
Type
conf
DOI
10.1109/CICC.1991.164001
Filename
164001
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