• DocumentCode
    2061261
  • Title

    3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS

  • Author

    Jihwan Kim ; Balankutty, Ajay ; Elshazly, Amr ; Yan-Yu Huang ; Hang Song ; Kai Yu ; O´Mahony, Frank

  • Author_Institution
    Intel, Hillsboro, OR, USA
  • fYear
    2015
  • fDate
    22-26 Feb. 2015
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Emerging standards in wireline communication are defining a path to data-rates of 40Gb/s and beyond. Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for some applications and loss profiles. Recently, several transmitters have been reported that operate between 28 and 60Gb/s using NRZ or PAM4 modulation exclusively. However, high-speed SerDes building blocks that support both a wide frequency range and multiple forms of modulation provide more compatibility between components and avoid the development of multiple IPs. In addition, these blocks must continue to scale into the next-generation of CMOS process technologies to lower the cost by reducing area and power consumption. This paper presents a dual-mode transmitter (TX) implemented in 14nm CMOS that supports both NRZ and PAM4 modulations and operates from 16 to 40Gb/s. The TX incorporates a 4-tap NRZ FIR filter that is reconfigurable to drive PAM4 levels, quarter-rate clocking with a high-bandwidth 4:1 serializer, a duty-cycle and quadrature-error correction circuit with statistical phase error detection, and compact, multi-layer T-coils for pad capacitance (Cpad) reduction.
  • Keywords
    CMOS integrated circuits; FIR filters; error correction; error detection; power consumption; radio transmitters; CMOS integrated circuit; CMOS process technology; NRZ FIR filter; NRZ signaling; PAM4 dual-mode transmitter; high-speed SerDes building blocks; power consumption; quadrature error correction; quarter-rate NRZ; radio transmitters; signal integrity constraints; size 14 nm; statistical phase error detection; wireline communication; CMOS integrated circuits; Clocks; Delays; Modulation; Optical signal processing; Resistors; Transmitters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid- State Circuits Conference - (ISSCC), 2015 IEEE International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4799-6223-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2015.7062925
  • Filename
    7062925