Automatic scheduling and verification of the control function of flexible assembly cells in an information reuse environment

Formal synthesis and verification of control programs in manufacturing applications are currently undeveloped areas. Today, new control programs are most often debugged on the shop floor, and when formal methods are used, the result is often a control function that is impossible to interpret by the operators. We present a method for synthesis of the control function of a PLC program. By combining supervisory control theory with a hierarchical program structure, in which the control function is separated from the rest of the PLC program, the generated control function combines the benefits of a traditional supervisor, e.g. non-blocking, optimality and flexibility, with simplicity and clearness. The traditional coding is replaced by information reuse and configuration of program components, instantiated from a software library