DocumentCode :
2062224
Title :
Pre-Route Interconnect Capacitance and Power Estimation in FPGAs
Author :
Bhoj, Shilpa ; Bhatia, Dinesh
Author_Institution :
Univ. of Texas at Dallas, Richardson
fYear :
2007
fDate :
27-29 Aug. 2007
Firstpage :
159
Lastpage :
164
Abstract :
The increase in functional complexity and performance requirements of reconfigurable fabrics has necessitated the early estimation of power distribution to explore power aware architectures and design techniques. In this work, we make several contributions to interconnect power estimation in FPGAs. First we present a probabilistic methodology that uses demand, a parameter reflecting the probable usage of a routing resource, to estimate interconnect capacitance and dynamic power dissipation. We then extend this model to estimate static power distribution of interconnect resources. Finally, the framework of our model also allows us to estimate spatial power distribution. Our results indicate accurate predictions with average errors of 7, 11 and 7 percent for capacitance, dynamic and static power respectively.
Keywords :
field programmable gate arrays; power aware computing; reconfigurable architectures; FPGA; dynamic power dissipation; interconnect power estimation; power aware architectures; power distribution estimation; power estimation; preroute interconnect capacitance; reconfigurable fabrics; Capacitance; Energy management; Field programmable gate arrays; Integrated circuit interconnections; Power dissipation; Power distribution; Power generation; Power system interconnection; Routing; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
Type :
conf
DOI :
10.1109/FPL.2007.4380641
Filename :
4380641
Link To Document :
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