An effective high-level synthesis approach for dynamically reconfigurable systems

There are two difficult issues in the formal treatment of the high-level synthesis of dynamically reconfigurable systems: (1) formulation of the time-varying mapping, and (2) reconfiguration overhead optimization with design space exploration. In this paper, we present a graph-based algorithmic framework to define and solve these problems. We use an extended control data flow graph (ECDFG) as an intermediate representation which abstracts the temporal nature of a system in terms of the sensitization of paths in the data flow. Based on this model, we propose a confguration bundling-driven module allocation technique that can be used for component clustering for optimizing the reconfiguration overhead. Our graph-based algorithmic model allows the tasks of high-level synthesis to be specified as an optimization problem. We solve the optimization problem through a genetic algorithm, which performs temporal partitioning, module allocation and scheduling simultaneously to maximize resource usage and minimize the reconfiguration overhead.