An embedded RISC core design for variable length coding

The increasing use of the embedded RISC core (ERC) has become a popular trend for embedded systems. In this paper, an ERC design for variable length coding (VLC) applications is presented. The initial ERC architecture is firstly selected by analyzing the complexity and parallelism of the VLC algorithm. Consequently the software and hardware architecture of the ERC are optimized in terms of the VLC characteristics. A field programmable gate array (FPGA) prototype is established for logic verification of the ERC, which is followed by the implementation of the ERC on a soft-core. The proposed ERC can be widely used in video coding and image compression applications, such as digital TV, videoconferencing and multimedia communications.