DocumentCode :
2062526
Title :
On the Feasibility of Early Routing Capacitance Estimation for FPGAs
Author :
Clarke, Jonathan A. ; Constantinides, George A. ; Cheung, Peter Y K
Author_Institution :
Imperial Coll. London, London
fYear :
2007
fDate :
27-29 Aug. 2007
Firstpage :
234
Lastpage :
239
Abstract :
Knowing the capacitance of circuit nets in an FPGA design is essential when computing the dynamic power consumed by switching these nets. Before a circuit is placed, however, there is little information available to allow the capacitance of routing wires to be estimated. In this paper we study the feasibility of estimating routing capacitance before RTL-synthesis to allow high-level power consumption optimization algorithms to be able to target routing power. We propose a novel method for estimating the capacitance of nets before RTL-synthesis and show that this method improves the accuracy and the rank ordering of the net-by-net estimates made over existing fan-out based techniques.
Keywords :
field programmable gate arrays; logic design; network routing; power aware computing; power consumption; FPGA design; RTL-synthesis; circuit nets; high-level power consumption optimization algorithms; routing capacitance estimation; routing wires; Adaptive filters; Circuit simulation; Field programmable gate arrays; Finite impulse response filter; Frequency estimation; Logic; Parasitic capacitance; Routing; Switching circuits; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
Type :
conf
DOI :
10.1109/FPL.2007.4380653
Filename :
4380653
Link To Document :
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