DocumentCode :
2062666
Title :
Disjoint Pattern Enumeration for Custom Instructions Identification
Author :
Yu, Pan ; Mitra, Tulika
Author_Institution :
Nat. Univ. of Singapore, Singapore
fYear :
2007
fDate :
27-29 Aug. 2007
Firstpage :
273
Lastpage :
278
Abstract :
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analysis of the program´s dataflow graphs. The characteristics of certain applications and the modern compiler optimization techniques (e.g., loop unrolling, region formation, etc.) have lead to substantially larger dataflow graphs. Hence, it is computationally expensive to automatically select the optimal set of custom instructions. Heuristic techniques are often employed to quickly search the design space. In order to leverage full potential of custom instructions, our previous work proposed an efficient algorithm for exact enumeration of all possible candidate instructions (or patterns) given the dataflow graphs. But the algorithm was restricted to connected computation patterns. In this paper, we describe an efficient algorithm to generate all feasible disjoint patterns starting with the set of feasible connected patterns. Compared to the state-of-the-art technique, our algorithm achieves orders of magnitude speedup while generating the identical set of candidate disjoint patterns.
Keywords :
application specific integrated circuits; data flow graphs; instruction sets; microprocessor chips; optimisation; optimising compilers; application-specific custom instructions; compiler optimization; core instruction set architecture; custom instructions identification; disjoint pattern enumeration; extensible processors; heuristic techniques; program dataflow graphs; Application software; Application specific integrated circuits; Application specific processors; Computer aided instruction; Computer architecture; Computer science; Embedded computing; Optimizing compilers; Scalability; Space exploration; ASIPs; custom instruction; customizable processors; instruction-set extensions; subgraph enumeration algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
Type :
conf
DOI :
10.1109/FPL.2007.4380659
Filename :
4380659
Link To Document :
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