Self-controllable voltage level circuit for low power, high speed 7T SRAM cell at 45 nm technology

The trend of decreasing device size and increasing chip densities involving several hundred millions of transistors per chip has resulted in tremendous increase in design complexity. Power dissipation occurs in various forms, such as dynamic, sub threshold leakage, gate leakage, etc. and there is need to reduce each of these. A low leakage power, 45-nm 7T SRAM is designed in this paper. The stand-by leakage power of 7T sram is reduced by incorporating a newly-developed leakage current reduction circuit called a “Self-controllable Voltage Level (SVL)” circuit. Simulation result of 7t SRAM design using CADENCE tool shows the reduction in total average power. In this design seven Transistor (7T) gated-ground sram is used as a Load Circuit. The Cadence Virtuoso simulation in standard 45 nm CMOS technology confirms all results obtained for this paper.