10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS

Author

Gharibdoust, Kiarash ; Tajalli, Armin ; Leblebici, Yusuf

Author_Institution

EPFL, Lausanne, Switzerland

fYear

2015

fDate

22-26 Feb. 2015

Firstpage

1

Lastpage

3

Abstract

Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing system. Memory systems typically apply dual in-line memory modules (DIMMs) because of their high capacity and low cost. However, the multi-drop bus (MDB) interface between these units and the controller is challenging for bandwidth and power reasons. Multi-tone signaling has promising characteristics for this type of interface [1]. To keep up with the ever growing demand for higher bandwidth in multi-drop buses, we develop a 7.5Gb/s (3.75Gb/s/pin) NRZ/multi-tone (NRZ/MT) transceiver with a total link power efficiency of 1mW/Gb/s.

Keywords

CMOS integrated circuits; data communication; radio links; radio transceivers; telecommunication signalling; CMOS technology; DIMM; MDB interface; bit rate 7.5 Gbit/s; data communication bandwidth; data processing efficiency; dual in-line memory module; link power efficiency; mixed NRZ-multitone serial-data transceiver; multidrop bus interface; multidrop memory interface; multitone signaling; power 7.5 mW; size 40 nm; Band-pass filters; Clocks; Computer architecture; Mixers; Optical signal processing; Receivers; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid- State Circuits Conference - (ISSCC), 2015 IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4799-6223-5

Type

conf

DOI

10.1109/ISSCC.2015.7062985

Filename

7062985