DocumentCode :
2062983
Title :
Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs
Author :
Paulsson, K. ; Hübner, M. ; Auer, G. ; Dreschmann, M. ; Chen, L. ; Becker, J.
Author_Institution :
Univ. Karlsruhe (TH), Karlsruhe
fYear :
2007
fDate :
27-29 Aug. 2007
Firstpage :
351
Lastpage :
356
Abstract :
The exploitation of dynamic and partial hardware reconfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual internal configuration port for the Spartan III family of FPGAs. The configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
Keywords :
computer interfaces; field programmable gate arrays; reconfigurable architectures; Virtex II/IV/V architecture; Xilinx Spartan III FPGA architecture; dynamic partial self-reconfigurable system; hardware reconfigurable measurement system; virtual internal configuration access port; Automotive engineering; Computer architecture; Cost function; Energy consumption; Field programmable gate arrays; Hardware; Information processing; Reconfigurable architectures; Space technology; Vehicle dynamics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
Type :
conf
DOI :
10.1109/FPL.2007.4380671
Filename :
4380671
Link To Document :
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