• DocumentCode
    2063109
  • Title

    A new approach to chip size package using meniscus soldering and FPC-bonding

  • Author

    Kallmayer, Christine ; Jung, Erik ; Kasulke, Paul ; Azadeh, Ramin ; Azdasht, Ghassem ; Zakel, Elke ; Reichl, Herbert

  • Author_Institution
    Microperipheric Center, Tech. Univ. Berlin, Germany
  • fYear
    1997
  • fDate
    18-21 May 1997
  • Firstpage
    114
  • Lastpage
    119
  • Abstract
    A Chip Size Package was developed using a tape carrier for interconnection and redistribution of the pads of high pincount IC´s. The complete package is 650 μm thick including a 550 μm thick chip and a 100 μm thick flexible carrier. A three layer tape with gold or gold/nickel surface finish on the copper layer was used as flexible interposer. The production line which was established includes a low cost bumping on wafer level. The chips were provided with electroless Ni bumps on which a layer of eutectic Au-Sn solder was deposited by meniscus soldering. The bonding of these bumps to the flexible substrate was performed by FPC technology, a laser bonding method. Mechanical stability between the tape and the chip was achieved by application of a low stress adhesive prior to bonding. In a last step solder balls were placed on the tape and reflowed using a novel solder ball placement machine with an incorporated laser reflow unit. The package obtained is fully surface mount compatible, allowing easy processability
  • Keywords
    integrated circuit interconnections; integrated circuit packaging; laser beam applications; reflow soldering; surface mount technology; 100 micron; 550 micron; 650 micron; FPC-bonding; chip size package; fibre push connection; flexible interposer; flexible substrate; high pincount IC; laser bonding method; laser reflow unit; low cost bumping; meniscus soldering; processability; production line; reflow solder; surface mount compatible package; tape carrier; three layer tape; Copper; Costs; Flexible printed circuits; Gold; Nickel; Packaging; Production; Soldering; Surface finishing; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 1997. Proceedings., 47th
  • Conference_Location
    San Jose, CA
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-3857-X
  • Type

    conf

  • DOI
    10.1109/ECTC.1997.606155
  • Filename
    606155