A high performance motion vector processor IP design for H.264/AVC

Author

Yoo, Kiwon ; Park, Seungho ; Ko, Hyunsuk ; Sohn, Kwanghoon

Author_Institution

Digital Media R&D Center, Samsung Electron., Suwon

fYear

2008

fDate

14-16 April 2008

Firstpage

1

Lastpage

4

Abstract

In this paper, the world´s first hardware design of the motion vector processor of H.264/AVC and its FPGA implementation are presented. It aims at a low-cost high-throughput design for HD1080 (1920 times 1088) at 60 frames per second (fps) in High Profile (HP) H.264/AVC codec with Level 4.2. For this, deterministic processing loops control scheme and a novel 4 times 4 processing order substituting for the conventional double-Z one are presented to attain a high-throughput design. In addition, for maximizing hardware utilization and getting a low-cost design, two processing elements dedicated to motion vector derivation are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at 266 MHz and was completely conformed for Allegro compliance bitstreams on an FPGA platform.

Keywords

SRAM chips; codecs; field programmable gate arrays; logic gates; video coding; FPGA implementation; H.264/AVC codec; HD1080; SRAM; deterministic processing loops control scheme; hardware design; hardware utilization; logic gates; motion vector processor IP design; Automatic voltage control; Codecs; Field programmable gate arrays; Hardware; Logic design; Logic gates; Process control; Process design; Random access memory; Vector processors;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2008. ISCE 2008. IEEE International Symposium on

Conference_Location

Vilamoura

Print_ISBN

978-1-4244-2422-1

Electronic_ISBN

978-1-4244-2422-1

Type

conf

DOI

10.1109/ISCE.2008.4559504

Filename

4559504