Title :
Dynamic Voltage Scaling in a FPGA-Based System-on-Chip
Author :
Nunez-Yanez, Jose Luis ; Chouliaras, Vassilios ; Gaisler, Jiri
Author_Institution :
Bristol Univ., Bristol
Abstract :
This paper presents a DVS (Dynamic Voltage Scaling) enabled SoC (System-on-Chip) processing platform based on the Leon3 open-source processor and dynamically reconfigurable clock synthesis technology available in Virtex-4 Xilinx FPGAs. A special DVS monitor unit maintains correct operation of the processor core at a given voltage by tracking the behavior of an internal delay line and stopping the processor clock through a digital clock management (DCM) macroblock when a timing error is about to occur. Upon detection of a new valid working point the DVS monitor unit reconfigures the main DCM to synthesize a new frequency-adjusted CPU clock signal and reactivates the processor. The energy savings and operation range of the technology are evaluated in the context of video coding applications by executing different motion estimation kernels.
Keywords :
clocks; field programmable gate arrays; power aware computing; reconfigurable architectures; system-on-chip; FPGA-based system-on-chip; Leon3 open-source processor; Virtex-4 Xilinx FPGA; digital clock management; dynamic voltage scaling; dynamically reconfigurable clock synthesis technology; frequency-adjusted CPU clock signal; internal delay line behavior tracking; motion estimation kernel; processor clock; processor core; timing error; video coding; Clocks; Delay lines; Dynamic voltage scaling; Error correction; Field programmable gate arrays; Monitoring; Open source software; System-on-a-chip; Timing; Voltage control;
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
DOI :
10.1109/FPL.2007.4380689
