A high throughput FPGA embedded DSP architecture design

To meet the increasing computational requirements in Field Programmable Gate Array (FPGA) devices, high performance DSP core is needed to make up the disadvantage of traditional Configurable Logic Blocks (CLB) in computing. This paper presents a novel DSP architecture with high throughput capability. In Arithmetic Logical Unit (ALU), we implement a 6-stage pipelined multiplier to enhance data throughput, and an adder which supports the Single Instruction Multiple Data (SIMD) feature to provide data level parallelism. A cascade carry signal is implemented in control logic to avoid overflow error. Performance of the designed DSP core is evaluated against the XtremeDSP core embedded in Xilinx FPGA devices. Comparison result shows 2x higher performance than the XtremeDSP in average.