A trainable analog neural chip for image compression

Author

Chang, Chia-Fen ; Sheu, Bing J. ; Fang, Wai-Chi ; Choi, Joongho

Author_Institution

Univ. of Southern California, Los Angeles, CA, USA

fYear

1991

fDate

12-15 May 1991

Abstract

Video motion estimation and high-ratio image compression are two key data processing steps for advanced television systems and imaging machines. The detailed circuit design of a vector quantization chip with the full-search scheme is presented. Each 5×5 image block with 256 pixel-gray levels can be quantized into the 6-bit codebook by a prototype chip of 4.6 mm×6.8 mm in a 2-μm scalable MOSIS technology. A speedup factor of 750 over a Sun-3/60 workstation has been obtained. Adaptive codebook learning can be performed with a digital coprocessor

Keywords

CMOS integrated circuits; application specific integrated circuits; bandwidth compression; computerised picture processing; data compression; neural nets; television systems; 2 micron; 4.6 mm; 6 bit; 6.8 mm; CMOS; adaptive codebook learning; advanced television systems; analog neural chip; circuit design; codebook; digital coprocessor; full-search scheme; high ratio compression; image compression; imaging machines; key data processing; prototype chip; scalable MOSIS technology; speedup factor; trainable chip; vector quantization chip; video motion estimation; Circuit synthesis; Data processing; Image coding; Motion estimation; Neural network hardware; Pixel; Prototypes; TV; Vector quantization; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164010

Filename

164010