Characterization and simulation of different 7T SRAM topologies

Static Random Access Memory (SRAM) units are often directly integrated onto the same die with the microprocessors and influence the design metrics significantly. SRAM often consumes large percentages of the die size and their leakages significantly contribute to the static power dissipation of those chips. The main objective of this article is to characterize the leakage and acces time(speed) of Six different 7T SRAM cells The simulation results indicate that the timing behavior of SRAM cells are largely the same but power dissipation, leakage power in particular, vary significantly in 45 nm technology.