Aggressive Loop Pipelining for Reconfigurable Architectures

Author

Menotti, Ricardo ; Marques, Eduardo ; Cardoso, João M P

Author_Institution

Sao Paulo Univ., Sao Carlos

fYear

2007

fDate

27-29 Aug. 2007

Firstpage

501

Lastpage

502

Abstract

In this work aims new techniques for mapping software loops to FPGAs. Extensive and aggressive use of pipelining techniques for achieving high performance solutions is the main goal. Those techniques are foreseen to effectively take advantage of the hardware synergies available in the current FPGA devices, especially the DSP blocks and the on-chip configurable memories.

Keywords

field programmable gate arrays; pipeline processing; reconfigurable architectures; aggressive loop pipelining; field programmable gate arrays; hardware synergy; reconfigurable architecture; software loop mapping; Clocks; Computer architecture; Counting circuits; Delay; Field programmable gate arrays; Hardware; Pipeline processing; Program processors; Reconfigurable architectures; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on

Conference_Location

Amsterdam

Print_ISBN

978-1-4244-1060-6

Electronic_ISBN

978-1-4244-1060-6

Type

conf

DOI

10.1109/FPL.2007.4380699

Filename

4380699

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2063709